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SEMICONDUCTOR
CDP6402, CDP6402C
CMOS Universal Asynchronous Receiver/Transmitter (UART)
Description
The CDP6402 and CDP6402C are silicon gate CMOS Universal Asynchronous Receiver/Transmitter (UART) circuits for interfacing computers or microprocessors to asynchronous serial data channels. They are designed to provide the necessary formatting and control for interfacing between serial and parallel data channels. The receiver converts serial start, data, parity, and stop bits to parallel data verifying proper code transmission, parity and stop bits. The transmitter converts parallel data into serial form and automatically adds start parity and stop bits. The data word can be 5, 6, 7 or 8 bits in length. Parity may be odd, even or inhibited. Stop bits can be 1, 1-1/2, or 2 (when transmitting 5-bit code). The CDP6402 and CDP6402C can be used in a wide range of applications including modems, printers, peripherals, video terminals, remote data acquisition systems, and serial data links for distributed processing systems. The CDP6402 and CDP6402C are functionally identical. They differ in that the CDP6402 has a recommended operating voltage range of 4V to 10.5V, and the CDP6402C has a recommended operating voltage range of 4V to 6.5V.
August 1996
Features
* Low Power CMOS Circuitry. . . . . . . . . . 7.5mW (Typ) at 3.2MHz (Max Freq.) at VDD = 5V * Baud Rate - DC to 200K Bits/s (Max) at. . . . . . . . . . . . . . 5V, 85oC - DC to 400K Bits/s (Max) at. . . . . . . . . . . . . . 10V, 85oC * 4V to 10.5 Operation * Automatic Data Formatting and Status Generation * Fully Programmable with Externally Selectable Word Length (5 - 8 Bits), Parity Inhibit, Even/Odd Parity, and 1, 1-1/2, or 2 Stop Bits * Operating Temperature Range - CDP6402D, CD . . . . . . . . . . . . . . . . . -55oC to +125oC - CDP6402E, CE . . . . . . . . . . . . . . . . . . -40oC to +85oC * Replaces Industry Type IM6402 and Compatible with HD6402
Ordering Information
PACKAGE
PDIP Burn-In SBDIP Burn-In -40oC to +85oC
TEMP. RANGE
-40oC to +85oC
5V/200K BAUD
CDP6402CE CDP6402CEX CDP6402CD
10V/400K BAUD
CDP6402E CDP6402D
PKG. NO. E40.6 D40.6
CDP6402CDX CDP6402DX
Pinout
(40 LEAD PDIP, SBDIP) TOP VIEW
VDD NC GND RRD RBR8 RBR7 RBR6 RBR5 RBR4 RBR3 RBR2 RBR1 PE FE OE SFD RRC DRR DR RRI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 TRC EPE CLS1 CLS2 SBS PI CRL TBR8 TBR7 TBR6 TBR5 TBR4 TBR3 TBR2 TBR1 TRO TRE TBRL TBRE MR
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) Harris Corporation 1996
File Number
1328.2
5-74
CDP6402, CDP6402C
TBR8 (MSB) TBR1 (LSB)
TRE TBRL TRC PARITY LOGIC STOP
TRANSMITTER BUFFER REGISTER TRANSMITTER TIMING AND CONTROL TRANSMITTER REGISTER MULTIPLEXER TRO START
CLS1 CLS2 CRL MR CONTROL REGISTER SBS EPE PI
RRI RRC DRR RECEIVER TIMING AND CONTROL STOP LOGIC PARITY LOGIC RECEIVER BUFFER REGISTER MULTIPLEXER START LOGIC RECEIVER REGISTER
SFD
THREE STATE BUFFERS
RRD
DR
OE
TBRE
FE
PE
RBR8 (MSB)
RBR1 (LSB)
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
5-75
CDP6402, CDP6402C
Absolute Maximum Ratings
DC Supply-Voltage Range, (VDD) CDP6402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +11V CDP6402C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5 to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . 100A Device Dissipation Per Output Transistor For TA = Full Package-Temperature Range (All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW Operating-Temperature Range (TA) Package Type D (SBDIP) . . . . . . . . . . . . . . . . . . -55oC to +125oC Package Type E (PDIP) . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 50 N/A SBDIP Package . . . . . . . . . . . . . . . . . . 55 15 Maximum Storage Temperature Range (TSTG) . . .-65oC to +150oC Maximum Lead Temperature (Soldering 10s): At Distance 1/16 1/32 inch (1.59 0.79mm) . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Operating Conditions At TA = Full Package-Temperature Range. For maximum reliability, operating conditions should be selected so
that operatIon is always within the following ranges: LIMITS CDP6402 PARAMETER DC Operating Voltage Range Input Voltage Range MIN 4 VSS MAX 10.5 VDD MIN 4 VSS CDP6402C MAX 6.5 VDD UNITS V V
Static Electrical Specifications at TA = -40oC to +85oC, VDD 10%, Except as noted
CONDITIONS CDP6402 VO (V) IDD Output Low Drive (Sink) Current IOL 0.4 0.5 Output High Drive (Source) Current IOH 4.6 9.5 Output Voltage LowLevel (Note 2) VOL Output Voltage High Level (Note 2) VOH Input Low Voltage VIL 0.5, 4.5 0.5, 9.5 VIN (V) 0, 5 0,10 0,5 0,10 0, 5 0,10 0, 5 0, 10 0, 5 0, 10 VDD (V) 5 10 5 10 5 10 5 10 5 10 5 10 (NOTE 1) TYP 0.01 1 4 7 -1.1 -2.6 0 0 5 10 LIMITS CDP6402C (NOTE 1) TYP 0.02 2.4 -1.1 0 5 -
PARAMETER Quiescent Device Current
MIN 2 5 -0.55 -1.3 4.9 9.9 -
MAX 50 200 0.1 0.1 0.8 0.2 VDD
MIN 1.2 -0.55 4.9 -
MAX 200 0.1 0.8 -
UNITS A A mA mA mA mA V V V V V V
5-76
CDP6402, CDP6402C
Static Electrical Specifications at TA = -40oC to +85oC, VDD 10%, Except as noted
CONDITIONS CDP6402 VO (V) VIH 0.5, 4.5 0.5, 9.5 Input Leakage Current IIN Any Input VIN (V) 0,5 0,10 Three-State Output Leakage Current IOUT 0, 5 0, 10 Operating Current (Note 2) IDD1 Input Capacitance Output Capacitance NOTES: 1. Typical values are for TA = 25oC and nominal VDD 2. IOL = IOH = 1A. 3. Operating current is measured at 200kHz or VDD = 5V and 400kHz for VDD = 10V, with open outputs (worst-case frequencies for CDP1802A system operating at maximum speed of 3.2MHz). CIN COUT 0, 5 0,10 0, 5 0,10 VDD (V) 5 10 5 10 5 10 5 10 (NOTE 1) TYP 10-4 10-4 10-4 10-4 1.5 10 5 10 (Continued)
LIMITS CDP6402C (NOTE 1) TYP 10-4 1.5 5 10
PARAMETER Input High Voltage
MIN VDD-2 7 -
MAX 1 2 1 10 - - 7.5 15
MIN VDD-2 -
MAX 1 1 7.5 15
UNITS V V A A A A mA mA pF pF
5-77
CDP6402, CDP6402C Description of Operation
Initialization and Controls A positive pulse on the MASTER RESET (MR) input resets the control, status, and receiver buffer registers, and sets the serial output (TRO) High. Timing is generated from the clock inputs RRC and TRC at a frequency equal to 16 times the serial data bit rate. The RRC and TRC inputs may be driven by a common clock, or may be driven independently by two different clocks. The CONTROL REGISTER LOAD (CRL) input is strobed to load control bits for PARITY INHIBIT (PI), EVEN PARITY ENABLE (EPE), STOP BIT SELECTS (SBS), and CHARACTER LENGTH SELECTS (CLS1 and CLS2). These inputs may be hand wired to VSS or VDD with CRL to VDD. When the initialization is completed, the UART is ready for receiver and/or transmitter operations. Transmitter Operation The transmitter section accepts parallel data, formats it, and transmits it in serial form (Figure 2) on the TRO terminal.
START BIT LSB 5 - 8 DATA BITS 1, 1-1/2 OR 2 STOP BITS FE, PE 1/2 CLOCK CYCLES
Receiver Operation Data is received in serial form at the RRl input. When no data is being received, RRI input must remain high. The data is clocked through the RRC. The clock rate is 16 times the data rate. Receiver timing is shown in Figure 4.
BEGINNING OF FIRST STOP BIT RRI RBRI-8, OE 8 1/2 TO 9 1/2 CLOCK CYCLES
DRR
DR
A
B
C
FIGURE 4. RECEIVER TIMING WAVEFORMS
MSB
PARITY
IF ENABLED
FIGURE 2. SERIAL DATA FORMAT
Transmitter timing is shown in Figure 3. (A) Data is loaded into the transmitter buffer register from the inputs TBR1 through TBR8 by a logic low on the TBRL input. Valid data must be present at least tDT prior to, and tTD following, the rising edge of TBRL. If words less than 8-bits are used, only the least significant bits are used. The character is right justified into the least significant bit, TBR1. (B) The rising edge of TBRL clears TBRE. 1/2 to 11/2 cycles later, depending on when the TBRL pulse occurs with respect to TRC, data is transferred to the transmitter register and TRE is cleared. TBRE is set to a logic High one cycle after that. Output data is clocked by TRC. The clock rate is 16 times the data rate. (C) A second pulse on TBRL loads data into the transmitter buffer register. Data transfer to the transmitter register is delayed until transmission of the current character is complete. (D) Data is automatically transferred to the transmitter register and transmission of that character begins.
TBRL
(A) A low level on DRR clears the DR line. (B) During the first stop bit data is transferred from the receiver register to the RB Register. If the word is less than 8 bits, the unused most significant bits will be a logic low. The output character is right justified to the least significant bit RBR1. A logic high on OE indicates overruns. An overrun occurs when DR has not been cleared before the present character was transferred to the RBR. (C) 1/2 clock cycle later DR is set to a logic high and FE is evaluated. A logic high on FE indicates an invalid stop bit was received. A logic high on PE indicates a parity error. Start Bit Detection The receiver uses a 16X clock for timing (Figure 5). The start bit could have occurred as much as one clock cycle before it was detected, as indicated by the shaded portion. The center of the start bit is defined as clock count 7 1/2. If the receiver clock is a symmetrical square wave, the center of the start bit will be located within 1/2 clock cycle 1/32 bit or 3.125%. The receiver begins searching for the next start bit at 9 clocks into the first stop bit.
COUNT 7 1/2 DEFINED CENTER OF START BIT
CLOCK TBRE 1-1/2 TO 2-1/2 CYCLES TRE TRO A B 1/2 TO 1-1/2 CYCLES 1 TO 2 CYCLES DATA C D END OF LAST STOP BIT 1/2 CLOCK RRI INPUT A START 7 1/2 CLOCK CYCLES 8 1/2 CLOCK CYCLES
FIGURE 5. START BIT TIMING WAVEFORMS
FIGURE 3. TRANSMITTER TIMING WAVEFORMS
5-78
CDP6402, CDP6402C
TABLE 1. CONTROL WORD FUNCTION CONTROL WORD CLS2 L L L L L L L L L L L L H H H H H H H H H H H H NOTE: X = Don't Care CLS1 L L L L L L H H H H H H L L L L L L H H H H H H PI L L L L H H L L L L H H L L L L H H L L L L H H EPE L L H H X X L L H H X X L L H H X X L L H H X X SBS L H L H L H L H L H L H L H L H L H L H L H L H DATA BITS 5 5 5 5 5 5 6 6 6 6 6 6 7 7 7 7 7 7 8 8 8 8 8 8 PARITY BIT ODD ODD EVEN EVEN DISABLED DISABLED ODD ODD EVEN EVEN DISABLED DISABLED ODD ODD EVEN EVEN DISABLED DISABLED ODD ODD EVEN EVEN DISABLED DISABLED STOP BIT (S) 1 1.5 1 1.5 1 1.5 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
5-79
CDP6402, CDP6402C
TABLE 2. FUNCTION PIN DEFINITION PIN 1 2 3 4 SYMBOL VDD N/C GND RRD Positive Power Supply No Connection Ground (VSS) A high level on RECEIVER REGISTER DISABLE forces the receiver holding register ouputs RBR1-RBR8 to a high impedance state. The contents of the RECEIVER BUFFER REGISTER appear on these three-state outputs. Word formats less than 8 characters are right justified to RBR1. DESCRIPTION
5
RBR8
6 7 8 9 10 11 12 13
RBR7 RBR6 RBR5 RBR4 RBR3 RBR2 RBR1 PE A high level on PARITY ERROR indicates that the received parity does not match parity programmed by control bits. The output is active until parity matches on a succeeding character. When parity is inhibited, this output is low. A high level on FRAMING ERROR indicates the first stop bit was invalid. FE will stay active until the next valid character's stop bit is received. A high level on OVERRUN ERROR indicates the data received flag was not cleared before the last character was transferred to the receiver buffer register. The Error is reset at the next character's stop bit if DRR has been performed (i.e., DRR; active low). A high level on STATUS FLAGS DISABLE forces the outputs PE, FE, OE, DR, TBRE to a high impedance state. The RECEIVER REGISTER CLOCK is 16X the receiver data rate. A low level on DATA RECEIVED RESET clears the data received output (DR), to a low level. A high level on DATA RECEIVED indicates a character has been received and transferred to the receiver buffer register. Serial data on RECEIVER REGISTER INPUT is clocked into the receiver register. A high level on MASTER RESET (MR) clears PE, FE, OE and DR, and sets TRE, TBRE, and TRO. TRE is actually set on the first rising edge of TRC after MR goes high. MR should be strobed after power-up. A high level on TRANSMITTER BUFFER REGISTER EMPTY indicates the transmitter buffer register has transferred its data to the transmitter register and is ready for new data. A low level on TRANSMITTER BUFFER REGISTER LOAD transfers data from inputs TBR1-TBR8 into the transmitter buffer register. A low to high transition on TBRL requests data transfer to the transmitter register. If the transmitter register is busy, transfer is automatically delayed so that the two characters are transmitted end to end. A high level on TRANSMITTER REGISTER EMPTY indicates completed transmission of a character including stop bits. See Pin 5 - RBR8
14
FE
15
OE
16
SFD
17 18 19
RRC DRR DR
20 21
RRl MR
22
TBRE
23
TBRL
24
TRE
5-80
CDP6402, CDP6402C
TABLE 2. FUNCTION PIN DEFINITION (Continued) PIN 25 26 SYMBOL TRO TBR1 DESCRIPTION Character data, start data and stop bits appear serially at the TRANSMITTER REGISTER OUTPUT. Character data is loaded into the TRANSMITTER BUFFER REGISTER via inputs TBR1-TBR8. For character formats less than 8 bits, the TBR8, 7, and 6 Inputs are ignored corresponding to the programmed word length.
27 28 29 30 31 32 33 34 35 36
TBR2 TBR3 TBR4 TBR5 TBR6 TBR7 TBR8 CRL PI SBS A high level on CONTROL REGISTER LOAD loads the control register. A high level on PARITY INHIBIT inhibits parity generation, parity checking and forces PE output low. A high level on STOP BIT SELECT selects 1.5 stop bits for a 5 character format and 2 stop bits for other lengths. These inputs program the CHARACTER LENGTH SELECTED. (CLS1 low CLS2 low 5 bits) (CLS1 high CLS2 low 6 bits) (CLS1 low CLS2 high 7 bits) (CLS1 high CLS2 high 8 bits). See Pin 37 - CLS2 When PI is low, a high level on EVEN PARITY ENABLE generates and checks even parity. A low level selects odd parity. The TRANSMITTER REGISTER CLOCK is 16X the transmit data rate. See Pin 26 - TBR1
37
CLS2
38 39
CLSl EPE
40
TRC
See Table 1 (Control Word Function)
5-81
CDP6402, CDP6402C
Dynamic Electrical Specifications
at TA = -40oC to +85oC, VDD 5%, tR, tF = 20ns, VIH = 0.7 VDD , VIL = 0.3 VDD , CL = 100pF LIMITS CDP6402 (NOTE 1) PARAMETER SYSTEM TIMING (See Figure 6) Minimum Pulse Width CRL Minimum Setup Time Control Word to CRL Minimum Hold Time Control Word after CRL Propagation Delay Time SFD High to SOD SFD Low to SOD tCRL 5 10 tCWC 5 10 tCCW 5 10 tSFDH 5 10 tSFDL 5 10 RRD High to Receiver Register High Impedance RRD Low to Receiver Register Active Minimum Pulse Width MR NOTES: 1. All measurements are made at the 50% point of the transition except three-state measurements. 2. Typical values for TA = 25oC and nominal VDD. 3. Maximum limits of minimum characteristics are the values above which all devices function. tRRDH 5 10 tRRDL 5 10 5 10 50 40 20 0 40 20 130 100 130 40 80 40 80 40 200 100 150 100 50 40 60 30 200 150 200 60 150 70 150 70 400 200 50 20 40 130 130 80 80 200 150 50 60 200 200 150 150 400 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VDD (V) (NOTE 2) TYP (NOTE 3) MAX CDP6402C (NOTE 2) TYP (NOTE 3) MAX UNITS
CONTROL INPUT WORD TIMING CONTROL WORD INPUT CONTROL WORD BYTE tCWC CRL tCRL STATUS OUTPUT TIMING STATUS OUTPUTS tSFDH SFD 90% 10% 70% 30% tSFDL tCCW
RECEIVER REGISTER DISCONNECT TIMING 90% 10% R BUS 7 R BUS 0 tRRDH RRD
70% 30% tRRDL
FIGURE 6. SYSTEM TIMING WAVEFORMS
5-82
CDP6402, CDP6402C
Dynamic Electrical Specifications at TA = -40oC to +85oC, VDD 5%, tR, tF = 20ns, VIH = 0.7 VDD , VIL = 0.3 VDD , CL = 100pF
LIMITS CDP6402 (NOTE 1) PARAMETER TRANSMITTER TIMING (See Figure 7) Minimum Clock Period (TRC) tCC 5 10 Minimum Pulse Width Clock Low Level tCL 5 10 Clock High Level tCH 5 10 TBRL tTHTH 5 10 Minimum Setup Time TBRL to Clock tTHC 5 10 Data to TBRL tDT 5 10 Minimum Hold-Time Data after TBRL tTD 5 10 Propagation Delay Time Clock to Data Start Bit tCD 5 10 Clock to TBRE tCT 5 10 TBRL to TBRE tTTHR 5 10 Clock to TRE tTTS 5 10 NOTES: 1. All measurements are made at the 50% point of the transition except three-state measurements. 2. Typical values for TA = 25oC and nominal VDD. 3. Maximum limits of minimum characteristics are the values above which all devices function. 300 150 330 100 200 100 330 100 450 225 400 150 300 150 400 150 300 330 200 330 450 400 300 400 ns ns ns ns ns ns ns ns 40 20 60 30 40 60 ns ns 175 90 20 0 275 150 50 40 175 20 275 50 ns ns ns ns 100 75 100 75 80 40 125 100 125 100 200 100 100 100 80 125 125 200 ns ns ns ns ns ns 250 125 310 155 250 310 ns ns VDD (V) (NOTE 2) TYP (NOTE 3) MAX CDP6402C (NOTE 2) TYP (NOTE 3) MAX
UNITS
5-83
CDP6402, CDP6402C
TRANSMITTER BUFFER REGISTER LOADED (NOTE 1) tCC tCH TRC tTHC TBRL tTHTH TRO tTTHR TBRE tTTS TRE T BUS 0 T BUS 7 tDT DATA tDT tCT tCD tCD 1ST DATA BIT tCL 1 TRANSMITTER SHIFT REGISTER LOADED (NOTE 2) 2 3 4 5 6 7 14 15 16 1 2 3
NOTES: 1. The holding register is loaded on the trailing edge of TBRL. 2. The transmitter shift register, if empty , is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + tTHC after the trailing edge of TBRL and transmission of a start bit occurs 1/2 clock period + tCD later. FIGURE 7. TRANSMITTER TIMING WAVEFORMS
tCC tCH RRC tDC (NOTE 1) RRI R BUS 0 R BUS 7 tCL 1 2 3 4
CLOCK 7 1/2 SAMPLE 5 6 7 16 1 2
CLOCK 7 1/2 LOAD HOLDING REGISTER 3 4 5 6 7 8 9
START BIT PARITY
STOP BIT 1 tCDV DATA
DR tDDA DRR tDD OE (NOTE 2) PE tCFE FE tCOE tCDA
tCPE
NOTES: 1. If a start bit occurs at a time less than tDC before a high-to-low transition of the clock, the start bit may not be recognized until the next high-to-low transition of the clock. The start bit may be completely asynchronous with the clock. 2. If a pending DA has not been cleared by a read of the receiver holding register by the time a new word is loaded into the receiver holding register, the OE signal will come true.. FIGURE 8. RECEIVER TIMING WAVEFORMS
5-84
CDP6402, CDP6402C
Dynamic Electrical Specifications at TA = -40oC to +85oC, VDD 5%, tR, tF = 20ns, VIH = 0.7 VDD , VIL = 0.3 VDD , CL = 100pF
LIMITS CDP6402 (NOTE 1) PARAMETERS RECEIVER TIMING (See Figure 8) Minimum Clock Period (RRC) tCC 5 10 Minimum Pulse Width Clock Low Level tCL 5 10 Clock High Level tCH 5 10 Data Received Reset tDD 5 10 Minimum Setup Time Data Start Bit to Clock tDC 5 10 Propagation Delay Time Data Received Reset to Data Received tDDA 5 10 Clock to Data Valid tCDV 5 10 Clock to DR tCDA 5 10 Clock to Overrun Error tCOE 5 10 Clock to Parity Error tCPE 5 10 Clock to Framing Error tCFE 5 10 NOTES: 1. All measurements are made at the 50% point of the transition except three-state measurements. 2. Typical values for TA = 25oC and nominal VDD. 3. Maximum limits of minimum characteristics are the values above which all devices function. 150 75 275 110 275 110 275 100 240 120 200 100 250 125 400 175 400 175 400 150 375 17 300 150 150 275 275 275 240 200 250 400 400 400 375 300 ns ns ns ns ns ns ns ns ns ns ns ns 100 50 150 75 100 150 ns ns 100 75 100 75 50 25 125 100 125 100 75 40 100 100 50 125 125 75 ns ns ns ns ns ns 250 125 310 155 250 310 ns ns VDD (V) (NOTE 2) TYP (NOTE 3) MAX CDP6402C (NOTE 2) TYP (NOTE 3) MAX
UNITS
5-85

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